1. Field of the Invention
The present invention relates to a redundant decoder, and more particularly to a redundant decoder having a fuse-controlled transistor.
2. Description of the Prior Art
Presently, there is a high demand for high-density memory such as DRAM arrays. One way to increase the yield is to design of redundant memory arrays. By repairing defective memory devices, the yield is increased. As shown in FIG. 1, a memory array generally comprises several row word lines like W0 and W1 of FIG. 1, and several column bit lines like BS0 of FIG. 1, locating the stored data address in the memory. In order to prevent the entire memory array from being discarded due to defective rows or the defective columns, a redundant device is installed in most current memory arrays. For example, if rows W0 and W1 are defective, then redundant rows RW0 and RW1 are used, or if column bit line BS0 is defective redundant column bit line RBS0 is used.
In addition, as illustrated in FIG. 2, a redundant decoder 2 of a conventional redundant device comprises the following:
A discharging device, such as an evaluating NMOS transistor 13 coupled to ground Vss having a gate terminal G1 for inputting an evaluating signal .o slashed. and a drain terminal coupled to source terminal of a pair of MOS transistors. The NMOS transistor 13 is turned on by the evaluating signal .o slashed. at an evaluating cycle EV, thereby providing a discharging path 11 used to discharge to ground Vss.
A precharging device, such as a PMOS transistor 10 coupled to a power source Vcc having a gate terminal G2 for inputting a precharging signal npre. The PMOS transistor 10 is turned on by the precharging signal npre at a precharging cycle PC, thereby providing a precharging voltage X to the power source Vcc.
A pair of fuses 12 and 14 having a first terminal A and two second terminals B1, B2, wherein, first terminal A has been precharged at the precharging voltage X on the precharging device 10.
A pair of MOS transistors, such as NMOS transistors 16, 18 having drain terminals B3, B4, a source terminal C, and gate terminals G3, G4. Drain terminals B3, B4 couple the second terminals B1, B2 of the fuse 12, 14, respectively. Gate terminals G3, G4 are used to receive the pair of complementary address bit signals cx, cxn, and whether the NMOS transistors 16, 18 are turned on or not can be decided by the logic value 1 or 0 of the pair of complementary address bit signals cx, cxn. Source terminal C couples to the evaluating device 13.
According to the redundant decoder 2, when memory cells of a memory array have defects, the corresponding defective address bit, such as the fuse 14 of cxn, has to be blown down (by laser) in order to form a open loop, but the fuse 12 remains in a closed loop. Later, when the address bit of an address signal cx=0 and its complementary address bit cxn=1 are inputted, transistor 18 turns on and transistor 16 turns off so that discharging path 11 is unavailable. Meanwhile, the potential of the first terminal A of the fuse 12 and 14 has been maintained at the precharging voltage X level on logic 1. Hence decision circuit 15 outputs a redundant flag according to the precharging voltage X level of logic 1, thereby recognizing the representing address bit of the inputting address signal as the defective address bit and replacing with redundant memory cell corresponding to the inputted defective address.
On the other hand, when the address bit cx=1 of the address signal and its complementary address bit cxn=0 are inputted, transistor 18 turns off and transistor 16 turns on so that discharging path 11 is available. Meanwhile, the potential of the voltage of the first terminal A of fuse 12 and 14 will be pulled down to ground Vss along the discharging path 11. Hence decision circuit 15 will not output the redundant flag, thereby recognizing the representing address bit of the inputting address signal as a non-defective address bit.
However, the problem of a conventional redundant decoder 2 is that fuse 12 and fuse 14 are located on the discharging path. Fuse resistance is not easily controlled. Therefore, the discharging speed is influenced. Moreover, the entire circuit may break down.